COREU1PHY-AR【PDF 1/8 页】IP MODULE COREU1PHY

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CoreU1PHY – UTOPIA Level 1 PHY Interface

Product Summary

Libero IDE and Industry Standard Synthesis and

Simulation Tools

Intended Use

RTL Version

– VHDL Source Code

Standard UTOPIA Level 1 PHY Interface to any

–

Core Synthesis and Simulation Scripts

ATM Link-Layer Device

Actel-Developed Testbench (VHDL) Fully

Supported by Industry-Standard Simulation Tools

Key Features

Standard 8-Bit, 25 MHz UTOPIA Level 1 PHY

Design Tools Support

Interface Complies with the ATM Forum UTOPIA

Specification, Level 1 Version 2.01 (af-phy-

0017.000)

Separate TX and RX Clocks and Interface Pins

Simulation: VITAL Compliant VHDL and OVI

Compliant Verilog Simulators

Synthesis: LeonardoSpectrum ? , Synplify ? , Design

Compiler ? , FPGA Compiler TM , and FPGA Express TM

Supports Cell-Level Handshake for 53- or 54-byte

ATM Cells with Automatic Add/Drop of UDF2 Field

in the ATM Header in 53-byte Mode

Contents

16-Bit (54-byte) User Interfaces Can be Used

Directly or Bolt-Up to One of Actel's ATM Cell

Buffer Blocks: ATMBUFx

General Description ...................................................

Device Requirements .................................................

UTOPIA Interface .......................................................

Supported Families

? Fusion

? ProASIC3/E

? ProASIC PLUS?

Axcelerator ?

Core Deliverables

User Interface .............................................................

Ordering Information ................................................

List of Changes ...........................................................

Datasheet Categories .................................................

General Description

Netlist Version

CoreU1PHY is a UTOPIA Level 1 PHY interface core that

–

Compiled RTL Simulation Model Fully

Supported in Actel Libero ? Integrated Design

Environment (IDE)

Structural VHDL and Verilog Netlists (with and

without I/O Pads) Compatible with Actel’s

Utopia

connects directly to any ATM link-layer (master) device

and user logic (or optional ATM cell buffer blocks) to

provide an interface between the link-layer device and a

non-standard physical layer device ( Figure 1 ).

CoreATMBUF3

Level 1

Link-Layer

Device

CoreU1PHY

CoreATMBUF3

User

Logic

Other

Device

Figure 1 ? Block Diagram

December 2005

? 2005 Actel Corporation

v 4 .0

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